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| DATASHEET 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE ICS1894-32 Description The ICS1894-32 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802.3. It is intended for RMII/MII, Node/Repeater applications and includes the Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The ICS1894-32 incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sub-layer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100MHz. The ICS1894-32 provides a Serial-Management Interface for exchanging command and status information with a Station-Management (STA) entity. The ICS1894-32 Media-Dependent Interface (MDI) can be configured to provide either half-duplex or full-duplex operation at data rates of 10 Mb/s or 100Mb/s. In addition, the ICS1894-32 includes a programmable LED and interrupt output function. The LED outputs can be configured through registers to indicate the occurance of certain events such as LINK, COLLISION, ACTIVITY, etc. The purpose of the programmable interrupt output is to notify the PHY controller device immediately when a certain event happens instead of having the PHY controller continuously poll the PHY. The events that could be used to generate interrupts are: receiver error, Jabber, page received, parallel detect fault, link partner acknowledge, link status change, auto-negotiation complete, remote fault, collision, etc. The ICS1894-32 has deep power modes that can result in significant power savings when the link is broken. Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers, network connected appliances, and industrial equipment. Features * Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. * Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. * 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant * MIIM (MDC/MDIO) management bus for PHY register configuration * RMII interface support with external 50 MHz system clock * Single 3.3V power supply * Highly configurable, supports: - Media Independent Interface (MII) - Auto-Negotiation with Parallel detection - Node applications, managed or unmanaged - 10M or 100M full and half-duplex modes - Loopback mode for Diagnostic Functions * * * * * * * Auto-MDI/MDIX crossover correction Low-power CMOS (typically 300 mW) Power-Down mode (typically 21mW) Clock and crystal supported in MII mode Programmable LEDs Interrupt output pin Fully integrated, DSP-based PMD includes: - Adaptive equalization and baseline-wander correction - Transmit wave shaping and stream cipher scrambler - MLT-3 encoder and NRZ/NRZI encoder * * * * * Core power supply (3.3 V) 3.3 V/1.8 V VDDIO operation supported Smart power control with deep power down feature Available in 32-pin (5mm x 5mm) QFN package, Pb-free Available in Industrial Temp and Lead Free IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 1 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Block Diagram 100Base-T 10/100 MII/RMII MAC Interface Interface MUX PCS * Framer * CRS/COL Detection * Parallel to Serial * 4B/5B PMA * Clock Recovery * Link Monitor * Signal Detection * Error Detection TP_PMD * MLT-3 * Stream Cipher * Adaptive Equalizer * Baseline Wander Correction Integrated Switch 10Base-T MII Extended Register Set Low-Jitter Clock Synthesizer Clock Smart Power Control Block Power TwistedPair Interface to Magnetics Modules and RJ45 Connector MII Management Interface Configuration and Status AutoNegotiation LEDs and PHY Address Pin Assignment P1/LED1 P0/LED0 REFOUT REFIN VDDD 25 TXD3 TXD2 TXD1 TP_AP TP_AN VSS VDD TP_BN TP_BP VDD TCSR 1 TXD0 TXEN SPEED/TXCLK NLG32 With Ground Connecting to Thermal Pad NOD/RXER ANSEL/RXCLK VDDIO RMII/RXDV FDPX/RXD0 9 17 VSS MDC AMDIX/RXD3 RESET_N P2/INT MDIO P3/RXD2 32-pin 5mm x 5mm QFN IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE RXTR1RXD1 2 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name TP_AP TP_AN VSS VDD TP_BN TP_BP VDD TCSR VSS RESET_N P2/INT MDIO MDC AMDIX/RXD3 P3/RXD2 RXTRI/ RXD1 FDPX/ RXD0 RMII/RXDV VDDIO ANSEL/ RXCLK NOD/ RXER SPEED/ TXCLK TXEN TXD0 VDDD TXD1 TXT2 TXD3 Pin Type1 AIO AIO Power AIO AIO Power AIO Pin Description Twisted pair port A (for either transmit or receive) positive signal Twisted pair port A (for either transmit or receive) negative signal 3.3V Power Supply Twisted pair port B (for either transmit or receive) negative signal Twisted pair port B (for either transmit or receive) positive signal 3.3V Power Supply Transmit Current bias pin, connected to Vdd and ground via resistors (see "Recommended Component Values" table and the "ICS1894-32 TCSR" figure). Hardware reset for the entire chip (active low) PHY address Bit 2 as input (during power on reset/hardware reset) Interrupt output as output (default active low, can be programmed to active high) Management Data Input/Output Management Data Clock AMDIX enable as input (during power on reset/hardware reset) Receive data Bit 3 in MII mode as output. PHY address Bit 3 as input (during power on reset/hardware reset) Receive data Bit 2 in MII mode as output. RX tri-state enable as input (during power on reset/hardware reset) Receive data Bit 1 in both RMII and MII mode as output. Full duplex enable as input (during power on reset/hardware reset) Receive data Bit 0 in both RMII and MII mode as output RMII/MII select as input (during power on reset/hardware reset) Receive data valid in MII mode and CRS_DV in RMII mode as output. 3.3 V/1.8 V IO Power Supply. Auto-negotiation enable as input (during power on reset/hardware reset) Receive clock in MII mode as output. Node/repeater select as input (during power on reset/hardware reset) Receive error in MII/RMII mode as output 10M/100M select as input (during power on reset/hardware reset) Transmit clock in MII mode as output Transmit enable in RMII/MII mode Transmit data Bit 0 in RMII/MII mode 3.3 V Power Supply Transmit data Bit 1 in RMII/MII mode Transmit data Bit 2 in MII mode Transmit data Bit 3 in MII mode Ground Connect to ground. Ground Connect to ground. Input IO/Ipd IO Input IO/Ipu IO/Ipd IO/Ipu IO/Ipu IO/Ipd Power IO/Ipu IO/Ipd IO/Ipu Input Input Power Input Input Input IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 3 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Pin Number 29 30 31 32 PADDLE Notes: Pin Name REFOUT REFIN P0/LED0 P1/LED1 VSS Pin Type1 Input IO IO Pin Description Output 25 MHz crystal output, floating in RMII mode 25 MHz crystal (or clock) input in MII mode. 50 MHz clock input in RMII mode. PHY address Bit 0 as input (during power on reset/hardware reset) and LED # 0 (function configurable, default is "activity/no activity") as output PHY address Bit 1 as input (during power on reset/hardware reset) and LED # 1 (function configurable, default is "10/100 mode") as output Ground Connect to ground. 1. AIO: Analog input/output PAD. IO: Digital input/output. IN/Ipu: Digital input with internal 20k pull-up. IN/Ipd: Digital input with internal 20k pull-down. IO/Ipu: Digital input/output with internal 20k pull-up. IO/Ipd: Digital input/output with internal 20k pull-down. 2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted. 3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY to the MAC. 4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted. 5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 4 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Strapping Options Pin Number 14 15 11 31 32 16 17 Pin Name AMDIX/RXD3 P3/RXD2 P2/INT P0/LED0 P1/LED1 RXTRI/RXD1 FDPX/RXD0 Pin Type1 IO/Ipu IO/Ipd IO/Ipd IO IO IO/Ipd IO/Ipu 1 = AMDIX enable 0 = AMDIX disable Pin Function The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external pull-up or pull-down to set address at start up. 1 = Receiver Tristate Enable; 0 = Receiver Tristate Disable 1=Full duplex 0=Half duplex Ignored if Auto negotiation is enabled 1 = RMII mode 0 = MII mode 1=Enable auto negotiation 0=Disable auto negotiation 0=Node mode 1=repeater mode 1=100M mode 0=10M mode Ignored if Auto negotiation is enabled 18 20 21 22 RMII/RXDV ANSEL/RXCLK NOD/RXER SPEED/TXCLK IO/Ipd IO/Ipu IO/Ipd IO/Ipu 1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise. 2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise. Functional Description The ICS1894-32 is an ethernet PHYceiver. During data transmission, it accepts sequential nibbles/di-bits from the MAC (Media Access Control), converts them into a serial bit stream, encodes them, and transmits them over the medium through an external isolation transformer. When receiving data, the ICS1894-32 converts and decodes a serial bit stream (acquired from an isolation transformer that interfaces with the medium) into sequential nibbles/di-bits. It subsequently presents these nibbles/di-bits to the MAC Interface. The ICS1894-32 implements the OSI model's physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard: * Physical Medium Dependent sublayer (PMD) * Auto-Negotiation sublayer The ICS1894-32 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1894-32 can interface directly with the MAC via MII/RMII interface signals. The ICS1894-32 transmits framed packets acquired from its MAC Interface and receives encapsulated packets from another PHY, which it translates and presents to its MAC Interface. Note: As per the ISO/IEC standard, the ICS1894-32 does not affect, nor is it affected by, the underlying structure of the MAC frame it is conveying. * Physical Coding sublayer (PCS) * Physical Medium Attachment sublayer (PMA) IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 5 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100Base-TX Operation During 100Base-TX data transmission, the ICS1894-32 accepts packets from the MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1894-32 encapsulates each MAC frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1894-32 replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC frame. When receiving data from the medium, the ICS1894-32 removes each SSD and replaces it with the pre-defined preamble pattern before presenting the data on the MAC Interface. When the ICS1894-32 encounters an ESD in the received data stream, signifying the end of the frame, it ends the presentation of data on the MAC Interface. Therefore, the local MAC receives an unaltered copy of the transmitted frame sent by the remote MAC. During periods when MAC frames are being neither transmitted nor received, the ICS1894-32 signals and detects the IDLE condition on the Link Segment. In the 100Base-TX mode, the ICS1894-32 transmit channel sends a continuous stream of scrambled ones to signify the IDLE condition. Similarly, the ICS1894-32 receive channel continually monitors its data stream and looks for a pattern of scrambled ones. The results of this signaling and monitoring provide the ICS1894-32 with the means to establish the integrity of the Link Segment between itself and its remote link partner and inform its Station Management Entity (SME) of the link status. to be established and then reported to the ICS1894-32's SME. Auto-Negotiation The ICS1894-32 conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Autonegotiation is enabled by either hardware pin strapping (pin 20) or software (register 0h bit 12). Auto-negotiation allows link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest. * * * * Priority 1: 100Base-TX, full-duplex Priority 2: 100Base-TX, half-duplex Priority 3: 10Base-T, full-duplex Priority 4: 10Base-T, half-duplex If auto-negotiation is not supported or the ICS1894-32 link partner is forced to bypass auto-negotiation, the ICS1894-32 sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the ICS1894-32 to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. 10Base-T Operation During 10Base-T data transmission, the ICS1894-32 inserts only the IDL delimiter into the data stream. The ICS1894-32 appends the IDL delimiter to the end of each MAC frame. However, since the 10Base-T preamble already has a Start-of-Frame delimiter (SFD), it is not required that the ICS1894-32 insert an SSD-like delimiter. When receiving data from the medium (such as a twisted-pair cable), the ICS1894-32 uses the preamble to synchronize its receive clock. When the ICS1894-32 receive clock establishes lock, it presents the preamble nibbles to the MAC Interface. In 10M operations, during periods when MAC frames are being neither transmitted nor received, the ICS1894-32 signals and detects Normal Link Pulses. This action allows the integrity of the Link Segment with the remote link partner MII Management (MIIM) Interface The ICS1894-32 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the ICS1894-32. An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Additional details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification. The MIIM interface consists of the following: * A physical connection that incorporates the clock line (MDC) and the data line (MDIO). * A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with one or more IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 6 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER ICS1894-32 devices. Each ICS1894-32 device is assigned a PHY address between 1 and 7 by the P[4:0] strapping pins. P3 and P4 address bits are hardcoded to `0' in design. additional registers are provided for expanded functionality. The ICS1894-32 supports MIIM in both MII mode and RMII mode. The following table shows the MII Management frame format for the ICS1894-32. * An internal addressable set of thirty-one 8-bit MDIO registers. Register [0:6] are required, and their functions are defined by the IEEE 802.3u Specification. The MII Management Frame Format Preamble Start of Frame Read Write 32 1's 32 1's 01 01 Read/Write PHY Address OP Code Bits [4:0] 10 01 00AAA 00AAA REG Address Bits [4:0] RRRRR RRRRR TA Z0 10 Data Bits [15:0] DDDDDDDD_DDDDDDDD DDDDDDDD_DDDDDDDD Idle Z Z Interrupt (INT) P2/INT (pin 11) is an optional interrupt signal that is used to inform the external controller that there has been a status update in the ICS1894-32 PHY register. Register 23 shows the status of the various interrupts while register 22 controls the enabling/disabling of the interrupts. MII Data Interface The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Specification. It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: * Supports 10Mbps and 100Mbps data rates. * Uses a 25MHz reference clock, sourced by the PHY. * Provides independent 4-bit wide (nibble) transmit and receive data paths. * Contains two distinct groups of signals: one for transmission and the other for reception. The ICS1894-32 is configured for MII mode upon power-up or hardware reset with the following: * A 25MHz crystal connected to REFIN, REFOUT (pins 30, 29), or an external 25MHz clock source (oscillator) connected to REFIN IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 7 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER MII Signal Definition The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information. MII Signal Name Direction (with respect to PHY, ICS1894-32 signal) Output Input Input Output Output Output Output Direction (with respect to MAC) Input Output Output Input Input Input Input, or (not required) Description TXCLK TXEN TXD[3:0] RXCLK RXDV RXD[3:0] RXER Transmit Clock (2.5MHz for 10Mbps; 25MHz for 100Mbps) Transmit Enable Transmit Data [3:0] Receive Clock (2.5MHz for 10Mbps; 25MHz for 100Mbps) Receive Data Valid Receive Data [3:0] Receive Error Transmit Clock (TXCLK) TXCLK is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0]. TXCLK is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. * In 10Mbps mode, RXCLK is recovered from the line while carrier is active. RXCLK is derived from the PHY's reference clock when the line is idle, or link is down. * In 100Mbps mode, RXCLK is continuously recovered from the line. If link is down, RXCLK is derived from the PHY's reference clock. RXCLK is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. Transmit Enable (TXEN) TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated prior to the first TXCLK following the final nibble of a frame. TXEN transitions synchronously with respect to TXCLK. Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0]. * In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), and remains asserted until the end of the frame. Transmit Data (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXCLK. When TXEN is asserted, TXD[3:0] are accepted for transmission by the PHY. TXD[3:0] is "00" to indicate idle when TXEN is de-asserted. Values other than "00" on TXD[3:0] while TXEN is de-asserted are ignored by the PHY. * In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXCLK. Receive Data (RXD[3:0]) RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY. Receive Clock (RXCLK) RXCLK provides the timing reference for RXDV, RXD[3:0], and RXER. Receive Error (RXER) RXER is asserted for one or more RXCLK periods to indicate that an error (e.g. a coding error or any error that a IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 8 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC. Reduced MII (RMII) Data Interface The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: * Supports 10Mbps and 100Mbps data rates. * Uses a single 50MHz reference clock provided by the MAC or the system board. * Provides independent 2-bit wide (di-bit) transmit and receive data paths. * Contains two distinct groups of signals: one for transmission and the other for reception. In RMII mode, a 50 MHz reference clock is connected to REFIN(pin 30). IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 9 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER RMII Signal Definition The following table describes the RMII signals. Refer to RMII Specification for detailed information. RMII Signal Name Direction (with respect to PHY, ICS1894-32 signal) Input Input Input Output Output Output Direction (with respect to MAC) Input or Output Output Output Input Input, or (not required) Input Description REFIN TX_EN TXD[1:0] RXD[1:0 RX_ER CRS_DV[RXDV] Synchronous 50 MHz clock reference for receive, transmit and control interface Transmit Enable Transmit Data [1:0] Receive Data [1:0] Receive Error Carrier Sense/Data Valid Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REFIN which presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble boundaries). If the PHY has additional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the PHY shall assert CRS_DV on cycles of REFIN which present the second di-bit of each nibble and deassert CRS_DV on cycles of REFIN which present the first di-bit of a nibble. The result is: Starting on nibble boundaries CRS_DV toggles at 25 MHz in 100Mb/s mode and 2.5 MHz in 10Mb/s mode when the Carrier event ends before the RX_DV signal internal to the PHY is deasserted (i.e. the FIFO still has bits to transfer when the carrier event ends.) Therefore, the MAC can accurately recover RX_DV and the Carrier event end time. During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REFIN, the data on RXD[1:0] shall be "00" until proper receive signal decoding takes place (see definition of RXD[1:0] behavior). *Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. Reference Clock (REFIN) REFIN is sourced by the MAC or system board. It is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER. Transmit Enable (TX_EN) TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated prior to the first REFIN following the final di-bit of a frame. TX_EN transitions synchronously with respect to REFIN. Transmit Data [1:0] (TXD[1:0]) TXD[1:0] transitions synchronously with respect to REFIN. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] is "00" to indicate idle when TX_EN is de-asserted. Values other than "00" on TXD[1:0] while TX_EN is de-asserted are ignored by the PHY. Carrier Sense/Data Valid (CRS_DV[RXDV]) CRS_DV, identified as RXDV (pin 18), shall be asserted by the PHY when the receive medium is non-idle. The specifics of the definition of idle for 10BASE-T and 100BASE-X are contained in IEEE 802.3 [1] and IEEE 802.3u [2]. CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be detected. Receive Data [1:0] (RXD[1:0]) RXD[1:0] transitions synchronously to REFIN. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other than "00" on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 10 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Receive Error (RX_ER) RX_ER is asserted for one or more REFIN periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously with respect to REFIN. While CRS_DV is de-asserted, RX_ER has no effect on the MAC. AMDIX_EN (Pin 14) AMDIX enable pin with 20 kOhm pull-up resistor AMDIX_EN [19:9] MDIO register 19h bit 9 MDI_MODE [19:8] MDIO register 19h bit 8 Auto-MDI/MDIX Crossover The ICS1894-32 includes the auto-MDI/MDIX crossover feature. In a typical CAT 5 Ethernet installation the transmit twisted pair signal pins of the RJ45 connector are crossed over in the CAT 5 wiring to the partners receive twisted pair signal pins and receive twisted pair to the partners transmit twisted pair. This is usually accomplished in the wiring plant. Hubs generally wire the RJ45 connector crossed to accomplish the crossover. Two types of CAT 5 cables (straight and crossed) are available to achieve the correct connection. The Auto-MDI/MDIX feature automatically corrects for miss-wired installations by automatically swapping transmit and receive signal pairs at the PHY when no link results. Auto-MDI/MDIX is automatic, but may be disabled for test purposes by writing MDIO register 19 Bits 9:8 in the MDIO register. The Auto-MDI/MDIX function is independent of Auto-Negotiation and preceeds Auto-Negotiation when enabled. Auto MDI/MDIX Table AMDIX_EN (pin 14) x x 0 1 Default 1 1 0 straight/cross (auto select) AMDIX_EN [Reg 19:9] 0 0 1 1 MDI_MODE [Reg 19:8] 0 1 x x Tx/Rx MDI Configuration straight cross straight straight/cross (auto select) Definitions: straight cross transmit = TP_AP & TP_AN receive = TP_BP & TP_BN transmit = TP_BP & TP_BN receive = TP_AP & TP_AN IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 11 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Power Management The ICS1894-32 supports a Deep Power Mode (DPD) that is enabled under the following conditions: 1. The Phy is not Receiving any signal from the partner (Link Down) 2. The MAC is not transmitting data to the Phy (TXEN Low) Once the above conditions are met, the Phy goes into DPD mode after 32s (typical). The logic internal to the device can be selectively shut down in DPD mode depending on Register 24 Bits 8-4. Block Diagram of the Different Sections of the PHY as Affected by Register 24 bits TPLL Controlled by Register 24.7 10/100M Drive Clock Reference Clock XMIT_DAC Controlled by Register 24.5 TX_STRUCTURE If XMIT_DAC is powered down, this block is High_Z OUT IN RX and Equalizer Controlled by Register 24.6 CDR Controlled by Register 24.4 Bias for 10/100M Vbg Bias for Rx BGAP Bias Current Clock Reference Interface The REFIN pin provides the ICS1894-32 Clock Reference Interface. The ICS1894-32 requires a single clock reference with a frequency of 25 MHz 50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1894-32 supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REFIN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 12 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Crystal or Oscillator Connection ICS1894CK-32 MII w/ Crystal Input REFOUT 29 25.000MHz REFIN 30 25 pF 25 pF ICS1894CK-32 REFOUT 29 NC CMOS 25.000 MHz 33 Ohm (optional) REFIN 30 MII w/ Oscillator Input 10 pF (optional) ICS1894CK-32 REFOUT 29 NC CMOS 50.000 MHz 33 Ohm (optional) REFIN 30 RMII w/ Oscillator Input 10 pF (optional) IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 13 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER If a crystal is used as the clocking source, connect it to both the REFIN (pin 30) and REFOUT (pin 29) pins of the ICS1894-32. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the load caps serve to adjust the final frequency of the crystal oscillation. Typical applications would use 25 pF load caps. The exact value will be affected by the board routing capacitance on REFIN and REFOUT pins. Smaller load capacitors raise the frequency of oscillation. Once the exact value of load capacitance is established it will be the same for all boards using the same specification crystal. The best way to measure the crystal frequency is to measure the frequency of TXCLK (pin 22) using a frequency counter with a 1 second gate time. Using the buffered output TXCLK prevents the crystal frequency from being affected by the measurement. The crystal specification is shown in the 25MHz Crystal Specification table. 25 MHz Crystal Specification Table Specifications Fundamental Frequency Freq. Tolerance Input Capacitance Symbol Minimum F0 Typical Maximum 25.00125 Unit MHz ppm pF 24.99875 25.00000 3 F/f Cin 50 25 MHz Oscillator Specification table Specifications Output Frequency Freq. Stability (including aging) Duty cycle CMOS level one-half VDD VIH VIL Period Jitter Input Capacitance Tjitter CIN 3 Symbol Minimum F0 Typical Maximum 25.00125 Unit MHz ppm % Volts 0.33 500 Volts pS pF 24.99875 25.00000 35 2.79 F/f Tw/T 50 65 50 MHz Oscillator Specification table Specifications Output Frequency Freq. Stability (including aging) Duty cycle CMOS level one-half VDD VIH VIL Period Jitter Input Capacitance Tjitter CIN 3 Symbol Minimum F0 Typical Maximum 50.0025 Unit MHz ppm % Volts 0.33 500 Volts pS pF 49.9975 50.00000 35 2.79 F/f Tw/T 50 65 Status Interface The ICS1894-32 has two multi-function configuration pins that report the PHY status by providing signals that are intended for driving LEDs. Configuration is set by Bank0 Register 20. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 14 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Pins for Monitoring the Data Link table Pin P0/LED0 P1/LED1 Status Events that drive the LEDs Link, Activity, Tx, Rx, COL, Mode, Dplx Link, Activity, Tx, Rx, COL, Mode, Dplx resistors to provide a designated status indicator as described in the Pins for Monitoring the Data Link table. Use 1K resistors. Caution: Pins listed in the Pins for Monitoring the Data Link table must not float. 4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For example, if a multi-function configuration pin is pulled down to ground through an LED and a current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the asserted state, the output is driven high. 5. Adding 10K resistors across the LEDs ensures the PHY address is fully defined during slow VDD power-ramp conditions. 6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII tri-stated.) Note: 1. During either power-on reset or hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1894-32 exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs. 2. A software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs. 3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the address of the ICS1894-32. LEDs may be placed in series with these The following figure shows typical biasing and LED connections for the ICS1894-32. ICS1894CK-32 P1/LED1 32 P0/LED0 31 VDD LED1 10K 1K 1K LED0 10K The above circuit decodes the PHY address = 1 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 15 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Register Map Register Address 0 1 2,3 4 5 6 7 8 9 through 15 16 through 31 Control Status PHY Identifier Register Name Basic / Extended Basic Basic Extended Extended Extended Extended Extended Extended Extended Extended Auto-Negotiation Advertisement Auto-Negotiation Link Partner Ability Auto-Negotiation Expansion Auto-Negotiation Next Page Transmit Auto-Negotiation Next Page Link Partner Ability Reserved by IEEE Vendor-Specific (IDT) Registers Register Description Bit 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Reset Loopback enable Speed select1 Auto-Negotiation enable Low-power mode Isolate Auto-Negotiation restart Duplex mode1 Collision test IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved Definition When Bit = 0 No effect Disable Loopback mode 10 Mbps operation Disable Auto-Negotiation Normal power mode No effect No effect Half-duplex operation No effect Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 When Bit = 1 Reset mode Enable Loopback mode 100 Mbps operation Enable Auto-Negotiation Low-power mode Isolate from MII Restart Auto-Negotiation Full-duplex operation Enable collision test N/A N/A N/A N/A N/A N/A N/A Access 2 RW RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO SF2 SC - - - - - SC - - - - - - - - - Default3 0 0 1 1 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0/4 Hex 3 Register 0h - Control IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 16 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Definition 100Base-T4 100Base-TX full duplex 100Base-TX half duplex 10Base-T full duplex 10Base-T half duplex IEEE reserved IEEE reserved IEEE reserved IEEE reserved MF Preamble suppression Auto-Negotiation complete Remote fault Auto-Negotiation ability Link status Jabber detect Extended capability When Bit = 0 Always 0. (Not supported.) Mode not supported Mode not supported Mode not supported Mode not supported Always 0 Always 0 Always 0 Always 0 PHY requires MF Preambles Auto-Negotiation is in process, if enabled N/A Link is invalid/down No jabber condition N/A N/A When Bit = 1 Access 2 RO CW CW CW CW CW CW CW CW RO RO RO RO RO RO RO SF2 - - - - - - - - - - LH LH - LL LH - Default3 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 Hex 7 Register 1h - Control Mode supported Mode supported Mode supported Mode supported N/A N/A N/A N/A PHY does not require MF Preambles Auto-Negotiation is completed Always 1: PHY has Auto-Negotiation ability Link is valid/established Jabber condition detected Always 1: PHY has extended capabilities 8 0 No remote fault detected Remote fault detected 9 Register 2h - PHY Identifier 2.15 2.14 2.13 2.12 2.11 2.10 2.9 2.8 2.7 2.6 2.5 2.4 OUI bit 3 | c OUI bit 4 | d OUI bit 5 | e OUI bit 6 | f OUI bit 7 | g OUI bit 8 | h OUI bit 9 | I OUI bit 10 | j OUI bit 11 | k OUI bit 12 | l OUI bit 13 | m OUI bit 14 | n N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A CW CW CW CW CW CW CW CW CW CW CW CW - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 17 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 2.3 2.2 2.1 2.0 3.15 3.14 3.13 3.12 3.11 3.10 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 4.15 4.14 4.13 4.12 4.11 4.10 4.9 4.8 Definition OUI bit 15 | o OUI bit 16 | p OUI bit 17 | q OUI bit 18 | r OUI bit 19 | s OUI bit 20 | t OUI bit 21 | u OUI bit 22 | v OUI bit 23 | w OUI bit 24 | x Manufacturer's Model Number bit 5 Manufacturer's Model Number bit 4 Manufacturer's Model Number bit 3 Manufacturer's Model Number bit 2 Manufacturer's Model Number bit 1 Manufacturer's Model Number bit 0 Revision Number bit 3 Revision Number bit 2 Revision Number bit 1 Revision Number bit 0 Next Page IEEE reserved Remote fault IEEE reserved IEEE reserved IEEE reserved 100Base-T4 100Base-TX, full duplex When Bit = 0 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A When Bit = 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Access 2 CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW R/W CW R/W CW CW CW CW R/W SF2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Default3 0 1 0 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 Hex 5 Register 3h - PHY Identifier F 4 5 0 Register 4h - Auto-Negotiation Advertisement Next page not supported Next page supported Always 0 Locally, no faults detected Always 0 Always 0 Always 0 Always 0. (Not supported.) Do not advertise ability N/A Local fault detected N/A N/A N/A N/A Advertise ability 0 1 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 18 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 Definition 10Base-T, full duplex 10Base-T half duplex Selector Field bit S4 Selector Field bit S3 Selector Field bit S2 Selector Field bit S1 Selector Field bit S0 When Bit = 0 Do not advertise ability Do not advertise ability IEEE 802.3-specified default IEEE 802.3-specified default IEEE 802.3-specified default IEEE 802.3-specified default N/A When Bit = 1 Advertise ability Advertise ability Advertise ability N/A N/A N/A N/A IEEE 802.3-specified default Next Page enabled N/A Remote fault detected N/A N/A N/A N/A Link partner is capable Link partner is capable Link partner is capable Link partner is capable N/A N/A N/A N/A IEEE 802.3 defined. Always 1. Access 2 R/W R/W R/W CW CW CW CW CW SF2 - - - - - - - - Default3 1 1 1 0 0 0 0 1 Hex E 100Base-TX, half duplex Do not advertise ability 1 Register 5h - Auto-Negotiation Link Partner Ability 5.15 5.14 5.13 5.12 5.11 5.10 5.9 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 Next Page Acknowledge Remote fault IEEE reserved IEEE reserved IEEE reserved 100Base-T4 100Base-TX, full duplex Next Page disabled Always 0 No faults detected Always 0 Always 0 Always 0 Always 0. (Not supported.) Link partner is not capable RO RO RO RO RO RO RO RO RO RO RO RO CW CW CW CW - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 100Base-TX, half duplex Link partner is not capable 10Base-T, full duplex 10Base-T, half duplex Selector Field bit S4 Selector Field bit S3 Selector Field bit S2 Selector Field bit S1 Selector Field bit S0 Link partner is not capable Link partner is not capable IEEE 802.3 defined. Always 0. IEEE 802.3 defined. Always 0. IEEE 802.3 defined. Always 0. IEEE 802.3 defined. Always 0. N/A IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 19 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 6.15 6.14 6.13 6.12 6.11 6.10 6.9 6.8 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6.0 Definition IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved Parallel detection fault Link partner Next Page able Next Page able Page received Link partner Auto-Negotiation able Next Page IEEE reserved Message Page Acknowledge 2 Toggle Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field When Bit = 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 No Fault Link partner is not Next Page able Local device is not Next Page able Next Page not received Link partner is not Auto-Negotiation able Last Page Always 0 Unformatted Page Cannot comply with Message Previous Link Code Word was zero Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A When Bit = 1 Access 2 CW CW CW CW CW CW CW CW CW CW CW RO RO RO RO RO SF2 - - - - - - - - - - - LH - - LH - Default3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Hex 0 Register 6h - Auto-Negotiation Expansion 0 0 Multiple technologies detected Link partner is Next Page able Local device is Next Page able Next Page received Link partner is Auto-Negotiation able Additional Pages follow N/A Message Page Can comply with Message Previous Link Code Word was one Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message 4 Register 7h - Auto-Negotiation Next Page Transmit 7.15 7.14 7.13 7.12 7.11 7.10 7.9 7.8 RW RO RW RW RO RW RW RW - - - - - - - - 0 0 1 0 0 0 0 0 0 2 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 20 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 Definition Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Next Page IEEE reserved Message Page Acknowledge 2 Toggle Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field When Bit = 0 Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Last Page Always 0 Unformatted Page Cannot comply with Message Previous Link Code Word was zero Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message When Bit = 1 Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Additional Pages follow N/A Message Page Can comply with Message Previous Link Code Word was one Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Access 2 RW RW RW RW RW RW RW RW SF2 - - - - - - - - Default3 0 0 0 0 0 0 0 1 Hex 0 1 Register 8h - Auto-Negotiation Next Page Link Partner Ability 8.15 8.14 8.13 8.12 8.11 8.10 8.9 8.8 8.7 8.6 8.5 8.4 RO RO RO RO RO RO RO RO RO RO RO RO - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 21 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 8.3 8.2 8.1 8.0 Definition Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field When Bit = 0 Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message When Bit = 1 Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Access 2 RO RO RO RO SF2 - - - - Default3 0 0 0 0 Hex 0 Register 9 through 15h - Reserved by IEEE Register 16h - Extended Control Register 16.15 16.14 16.13 16.12 16.11 16.10 16.9 16.8 16.7 16.6 16.5 16.4 16.3 16.2 16.1 16.0 17.15 17.14 17.13 17.12 Command Override Write enable ICS reserved ICS reserved ICS reserved ICS reserved PHY Address Bit 4 PHY Address Bit 3 PHY Address Bit 2 PHY Address Bit 1 PHY Address Bit 0 Stream Cipher Test Mode ICS reserved NRZ/NRZI encoding Transmit invalid codes ICS reserved Stream Cipher disable Data rate Duplex Auto-Negotiation Progress Monitor Bit 2 Auto-Negotiation Progress Monitor Bit 1 Normal operation Read unspecified NRZ encoding Disabled Read unspecified Stream Cipher enabled 10 Mbps Half duplex Test mode Read unspecified NRZI encoding Enabled Read unspecified Stream Cipher disabled 100 Mbps Full duplex Disabled Read unspecified Read unspecified Read unspecified Read unspecified Enabled Read unspecified Read unspecified Read unspecified Read unspecified RW RW/0 RW/0 RW/0 RW/0 RO RO RO RO RO RW RW/0 RW RW RW/0 RW RO RO RO RO SC - - - - - - - - - - - - - - - - - LM X LM X 0 0 0 0 0 0 0 L L L 0 - 1 0 0 0 - - 0 0 - 8 - - - Register 17h - Quick Poll Detailed Status Register Reference Decode Table Reference Decode Table Reference Decode Table Reference Decode Table IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 22 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 18.15 18.14 18.13 18.12 Definition Auto-Negotiation Progress Monitor Bit 0 100Base-TX signal lost 100BasePLL Lock Error False Carrier detect Invalid symbol detected Halt Symbol detected Premature End detected Auto-Negotiation complete 100Base-TX signal detect Jabber detect Remote fault Link Status Remote Jabber Detect Polarity reversed Data Bus Mode When Bit = 0 When Bit = 1 Access 2 RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0 R0 SF2 LM X LH LH LH LH LH LH - - LH LH LL LH LH - - Default3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - L Hex 0 Reference Decode Table Reference Decode Table Valid signal PLL locked Normal Carrier or Idle Valid symbols observed Normal data stream Auto-Negotiation in process Signal present No jabber detected Link is not valid No Remote Jabber Condition detected Normal polarity Signal lost PLL failed to lock False Carrier Invalid symbol received Stream contained two IDLE symbols Auto-Negotiation complete No signal present Jabber detected Link is valid Remote Jabber Condition Detected Polarity reversed 0 No Halt Symbol received Halt Symbol received 0 No remote fault detected Remote fault detected Register 18h - 10Base-T Operations Register - Bit18.13 is latched pin RXTRI Bit18.12 is latched SI [1x]=RMII mode [01]=SI mode (Serial interface mode) [00]=MII mode AMDIX disable RX output enable Vender reserved register access enable AMDIX enable RX tri-state for MII/RMII interface Vender reserved register (byte25~byte31) access disable Read unspecified Read unspecified Jabber Check disabled Read unspecified 18.11 18.10 18.9 AMDIXEN RXTRI REGEN RW RW RW - - - L L L - 18.8 18.7 18.6 18.5 18.4 TM_SWITCH ICS reserved ICS reserved Jabber inhibit ICS reserved Switch TMUX2 to TMUX1, test control Read unspecified Read unspecified Normal Jabber behavior Read unspecified RW RW/0 RW/0 RW RW/1 - - - - - 0 - - 0 1 - IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 23 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 18.3 18.2 18.1 18.0 19.15 19.14 19.13 19.12 19.11 Definition Auto polarity inhibit SQE test inhibit Link Loss inhibit Squelch inhibit Node Mode Hardware/Software Mode Speed Select Remote Fault Register Bank select When Bit = 0 Polarity automatically corrected Normal SQE test behavior Normal Link Loss behavior When Bit = 1 Polarity not automatically corrected SQE test disabled Link Always = Link Pass Access 2 RW RW RW RW RW RW RO RW RW SF2 - - - - - - - - - Default3 0 0 0 0 L L 0 0 0 Hex 0 Normal squelch behavior No squelch Node mode Use bit00.13 to select speed No faults detected Repeater mode Use real time input pin 22 only to select speed Remote fault detected Register 19h - Extended Control Register - [01]=Bank1, access register0x00~0x13 and ICS1893CF registers 0x14~0x1F [00]=Bank0, access register0x00~0x13, new defined registers 0x14~0x25 [1x]=Bank0, same as [00] Read unspecified See Table on page 11 See Table on page 11 Twisted Pair Signals are not Tri-Stated or No effect Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Do not automatically power down Read unspecified See Table on page 11 See Table on page 11 Twisted Pair Signals are Tri-Stated Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Power down automatically 2 19.10 19.9 19.8 19.7 ICS reserved AMDIX_EN MDI_MODE Twisted Pair Tri-State Enable, TPTRI ICS reserved ICS reserved ICS reserved ICS reserved ICS reserved ICS reserved Automatic 100Base-TX Power Down RO RW RW RW - - - - 0 1 0 0 0 19.6 19.5 19.4 19.3 19.2 19.1 19.0 RW RW RW RW RW RW RW - - - - - - - 0 0 0 0 0 0 1 1 Register 20h - Extended Control Register 20.15 20.14 20.13 20.12 Str_enhance ICS reserved ICS reserved Normal digital output strength Read unspecified Read unspecified Enhance digital output strength in 1.8V condition Read unspecified Read unspecified RW RW RW - - 0 0 1 1 3 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 24 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 20.11 20.10 20.9 20.8 20.7 20.6 Definition ICS reserved When Bit = 0 Read unspecified When Bit = 1 Read unspecified Access 2 RW SF2 - Default3 1 1 1 Hex F LED2 Mode 000 = Link Integrity 001 = activity/no activity 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 10/100 mode 110 = Full Duplex 111 = OFF (Default LED2) 000 = Link Integrity 001 = activity/no activity 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 10/100 mode (Default LED1) 110 = Full Duplex 111 = OFF 000 = Link Integrity 001 = activity/no activity (Default LED0) 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 10/100 mode 110 = Full Duplex 111 = LINK_STAT RW 1 1 1 E 20.5 20.4 20.3 LED1 Mode RW 1 0 1 9 20.2 20.1 20.0 LED0 Mode RW 0 0 1 Register 21h - Extended Control Register 21.15:0 RXER_CNT Receive error count for RMII mode RW 0 0 0 0 0 Register 22h - Extended Control Register 22.15 22.14 22.13 22.12 Interrupt output enable Interrupt flag read clear enable Interrupt polarity Interrupt flag auto clear enable Disable interrupt output Interrupt flag clear by read disable Output low when interrupt occur Interrupt flag unchanged when interrupt condition removed Enable interrupt output Interrupt flag clear by read enable Output high when interrupt occur Interrupt flag cleared when interrupt condition removed RW RW RW RW 0 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 25 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 22.11 Definition Interrupt flag re-setup enable When Bit = 0 Interrupt flag always cleared when write 1 to flag bit When Bit = 1 Interrupt flag remains unchanged when interrupt condition exists when a 1 is written to flag bit. Enable Deep power down wake up Interrupt Enable Deep power down Interrupt Enable Auto-Negotiation Complete Interrupt Enable Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt Access 2 RW SF2 Default3 0 Hex 0 22.10 22.9 22.8 22.7 22.6 22.5 22.4 22.3 22.2 22.1 22.0 Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Disable Deep power down wake up Interrupt Disable Deep power down Interrupt Disable Auto-Negotiation Complete Interrupt Disable Jabber Interrupt Disable Receive Error Interrupt Disable Page Received Interrupt Disable Parallel Detect Fault Interrupt Disable Link Partner Acknowledge Interrupt Disable Link Down Interrupt Disable Remote Fault Interrupt RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Disable Link Up Interrupt Enable Link Up Interrupt Register 23h - Extended Control Register 23.15:11 23.10 23.9 23.8 23.7 23.6 23.5 23.4 Reserved Deep power down wake up Interrupt Deep power down Interrupt Auto-Negotiation Interrupt Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt Reserved Deep power down wake up did not occur Deep power down did not occur Auto-Negotiation Complete did not occur Jabber did not occur Receive Error did not occur Page Receive did not occur Parallel Detect Fault did not occur Deep power down wake up occurred Deep power down occurred Auto-Negotiation Complete occurred Jabber occurred Receive Error occurred Page Receive occurred Parallel Detect Fault occurred RO RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC 0 0 0 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 26 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 23.3 Definition Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt Link Up Interrupt When Bit = 0 Link Partner Acknowledge did not occur Link Down did not occur Remote Fault did not occur Link Up did not occur When Bit = 1 Link Partner Acknowledge occurred Link Down occurred Remote Fault occurred Link Up occurred Access 2 RO/SC SF2 Default3 0 Hex 0 23.2 23.1 23.0 RO/SC RO/SC RO/SC 0 0 0 Register 24h - Extended Control Register 24.15:12 24.11:9 24.8 24.7 FIFO Half Reserved Deep Power down enable Tpll10_100 DPD Enable RMII FIFO half full bits ((n+3)*2 bit), RMII Reserved Deep power down(DPD) disable Don't power down 10/100 PLL in DPD mode Don't power down RX block in DPD mode Don't power down admix_dac block in DPD mode Deep power down(DPD) enable Controlled auto power down10/100 PLL in DPD mode Controlled auto power down of RX block in DPD mode Control auto power down of admix_dac block in DPD mode Control auto power down of CDR block in DPD mode RW RW RW RW 2 0 0 0 0 2 0 24.6 RX 100 DPD Enable RW 0 24.5 Admix_TX DPD Enable RW 0 24.4 Cdr100_cdr DPD Enable don't power down in DPD mod Reserved Reserved RW 0 24.3:0 0 0 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 27 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit Definition When Bit = 0 When Bit = 1 Access 2 SF2 Default3 Hex Register 25h - Extended Control Register 25.15:12 25.11 25.10 25.9 25.8 25.7 Reserved Reserved Reserved TX10BIAS_SET Reserved Reserved Reserved The normal output current of the Bias block for 10BaseT is 540uA. Changing the register can modify the current with a step size of 5% 000: output 80% current 001: output 85% current 010: output 90% current 011: output 95% current 100: output 100% current 101: output 105% current 110: output 110% current 111: output 115% current The normal output current of the Bias block for 100BaseTX is 180uA. Changing the register can modify the current with a step size of 5% 000: output 80% current 001: output 85% current 010: output 90% current 011: output 95% current 100: output 100% current 101: output 105% current 110: output 110% current 111: output 115% current This register controls the delay time of the digital control signal for xmit_dac. 00: Longest delay time (same as original design) 01: Long delay time 10: Short delay time 11: Shortest delay time Reserved RW RW RW RW 0 0 1 1 0 0 4 0 6 25.6 25.5 25.4 TX100BIAS_SET RW 1 0 0 25.3 25.2 OUTDLY_CTL RW 0 1 25.1 25.0 Reserved RW 0 1 Register 26 - 31h - Extended Control Register (Reserved) Note 1: Ignored if Auto negotiation is enabled. Note 2: CW = Command Override Write LH = Latching High LL = Latching Low LMX = Latching Maximum RO = Read Only RW = Read/Write RW/0 = Read/Write Zero RW/1 = Read/Write One SC = Self-clearing SF = Special Functions Note 3: L = Latched on power-up/hardware reset = the default state of the pin at reset IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 28 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC and AC Operating Conditions Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS1894-32. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter VDD (measured to VSS) Digital Inputs / Outputs Storage Temperature Junction Temperature Soldering Temperature Power Dissipation Rating -0.3 V to 3.6V -0.3 V to VDD +0.3 V -55 C to +150 C 125 C 260 C See section "DC Operating Conditions for Supply Current" Recommended Operating Conditions Parameter Ambient Operating Temperature - Commercial Ambient Operating Temperature - Industrial Power Supply Voltage (measured to VSS) Symbol TA TA VDD Min. 0 -40 Max. Units +70 +85 C C V +3.14 +3.47 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 29 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Recommended Component Values Parameter TCSR Resistor Value LED Resistor Value Minimum - Typical 1.82k to GND 18.2k to VDD 1k Maximum - Tolerance 1% - Units ICS1894-32 TCSR ICS1894CK-32 VDD 7 18.2K 1% TCSR 8 VDD 1.82K 1% Note: 1. The bias resistor network sets the 10baseT and 100baseTX output amplitude levels. 2. Amplitude is directly related to current sourced out of the TCSR pin. 3. Resistor values shown above are typical. User should check amplitudes and adjust for transformer effects. 4. The 18.2K resistor provides negative feedback to compensate for VDD changes. Reducing the value of this resistor will lower the 100baseT amplitude. Reducing the value of the resistor to ground on the other hand will increase the output signal amplitude. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 30 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC Operating Characteristics for Supply Current The table below lists the DC operating characteristics for the supply current to the ICS1894-32 under various conditions. Condition Autonegotiation 100BaseTX FD and Linked 10BaseTX FD and Linked Power Down (Reg0:11 = 1) VDDIO (V) 3.3 1.8 3.3 3.3 3.3 VDD and VDDD (V) 3.3 3.3 3.3 3.3 3.3 Current (mA) (typical) 68 66 102 97 16 Deep Power Down Current Consumption Table Case 1 Register 24:8 Register 24:7 Register 24:6 Register 24:5 Register 24:4 DPD Enable TPLL_100 DPD Enable RX_100 DPD Enable Admix_TX DPD Enable CDR100_cdr DPD Enable Current (mA) (typical) 68 39 26 24 Case 2 Case 3 Case 4 Case 5 16 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 31 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC Operating Characteristics for Inputs and Outputs Unless otherwise specified, the table below lists the 3.3V/1.8 V DC operating characteristics of the ICS1894-32 inputs and outputs. For 3.3 V Signals Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage For 1.8 V Signals Symbol VIH VIL VOH VOL Conditions Min. Max. Units 2.0 - - 0.8 - 0.4 V V V V IOH = -4 mA IOL = +4 mA 2.4 - Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VIH VIL VOH VOL Conditions Min. Max. Units 0.8 - - 0.7 - 0.1 V V V V IOH = -4 mA IOL = +4 mA 1.6 - IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 32 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC Operating Characteristics for REFIN The table below lists the 3.3V DC characteristics for the REFIN pin. Parameter Input High Voltage Input Low Voltage Symbol VIH VIL Min. 2.97 - Max. - 0.33 Units V V DC Operating Characteristics for MII Pins The table below lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1894-32. Parameter MII Input Pin Capacitance MII Output Pin Capacitance MII Output Drive Impedance Conditions - - VDDIO = 3.3V Min. - - - Typ. - - 20 Max. 8 14 - Units pF pF Timing Diagrams Timing for Clock Reference (REFIN) Pin The table below lists the significant time periods for signals on the clock reference (REFIN) pin. The REFIN Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2 t1 t2 Parameter REFIN Duty Cycle (MII) REFIN Period (MII) REFIN Duty Cycle (RMII) REFIN Period (RMII) Conditions - - - - Min. 45 - 45 - Typ. 50 40 50 20 Max. Units 55 - 55 - % ns % ns REFIN Timing Diagram t1 REFIN t2 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 33 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Timing for Transmit Clock (TXCLK) Pin The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pin. The Transmit Clock Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2a t2b Parameter TXCLK Duty Cycle TXCLK Period TXCLK Period Conditions - 100M MII (100Base-TX) 10M MII (10Base-T) Min. Typ. Max. 35 - - 50 40 400 65 - - Units % ns ns Transmit Clock Timing Diagram t1 TXCLK t2x Timing for Receive Clock (RXCLK) Pin The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pin. The Receive Clock Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2a t2b Parameter RXCLK Duty Cycle RXCLK Period RXCLK Period Conditions - 100M MII (100Base-TX) 10M MII (10Base-T) Min. Typ. Max. Units 35 - - 50 40 400 65 - - % ns ns Receive Clock Timing Diagram t1 RXCLK t2 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 34 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M MII: Synchronous Transmit Timing The table below lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: * * * * TXCLK TXD[3:0] TXEN TXER The 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2 Parameter TXD[3:0], TXEN, TXER Setup to TXCLK Rise TXD[3:0], TXEN, TXER Hold after TXCLK Rise Conditions - - Min. 15 0 Typ. - - Max. Units - - ns ns 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER t1 t2 10M MII: Synchronous Transmit Timing The table below lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: TXCLK TXD[3:0] TXEN TXER The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods. * * * * Time Period t1 t2 Parameter TXD[3:0], TXEN, TXER Setup to TXCLK Rise TXD[3:0], TXEN, TXER Hold after TXCLK Rise Conditions - - Min. 375 0 Typ. - - Max. Units - - ns ns IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 35 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M MII Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER t1 t2 100M/MII Media Independent Interface: Synchronous Receive Timing The table below lists the significant time periods for the MII/100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: RXCLK RXD[3:0] RXDV RXER The MII Interface: Synchronous Receive Timing figure shows the timing diagram for the time periods. * * * * Time Period t1 t2 Parameter RXD[3:0], RXDV, and RXER Setup to RXCLK Rise RXD[3:0], RXDV, and RXER Hold after RXCLK Rise Min. 10.0 10.0 Typ. - - Max. Units - - ns ns MII Interface: Synchronous Receive Timing RXCLK RXD[3:0] RXDV RXER t1 t2 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 36 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER MII Management Interface Timing The table below lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2 t3 t4 t5 t6 Parameter MDC Minimum High Time MDC Minimum Low Time MDC Period MDC Rise Time to MDIO Valid MDIO Setup Time to MDC MDIO Hold Time after MDC Conditions - - - - - - Min. 160 160 400 0 10 10 Typ. - - - - - - Max. Units - - - 300 - - ns ns ns ns ns ns MII Management Interface Timing Diagram MDC t1 t3 MDIO (Output) t2 t4 MDC MDIO (Input) t5 t6 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 37 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M Media Independent Interface: Receive Latency The table below lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: * TP_RX (that is, the MII TP_RXP and TP_RXN pins) * RXCLK * RXD The 10M MII Receive Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter First Bit of /5/ on TP_RX to /5/D/ on RXD Conditions Min. Typ. Max. 10M MII - 6.5 7 Units Bit times 10M MII Receive Latency Timing Diagram TP_RX RXCLK RXD 5 5 5 D t1 Manchester encoding is not shown. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 38 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M Media Independent Interface: Transmit Latency The table below lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: * * * * TXEN TXCLK TXD (that is, TXD[3:0]) TP_TX (that is, TP_TXP and TP_TXN) The 10M MII Transmit Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter TXD Sampled to MDI Output of First Bit Conditions 10M MII Min. Typ. Max. - 1.2 2 Units Bit times 10M MII Transmit Latency Timing Diagram TXEN TXCLK TXD 5 5 5 TP_TX t1 Manchester encoding is not shown. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 39 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M / MII Media Independent Interface: Transmit Latency The table below lists the significant time periods for the MII/100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: * * * * TXEN TXCLK TXD (that is, TXD[3:0]) TP_TX (that is, TP_TXP and TP_TXN) The MII/100M Stream Interface Transmit Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter TXEN Sampled to MDI Output of First Bit of /J/ Conditions MII mode Min. Typ. - 2.8 Max. 3 Units Bit times The IEEE maximum is 18 bit times. MII/100M Stream Interface Transmit Latency Timing Diagram TXEN TXCLK TXD Preamble /J/ Preamble /K/ TP_TX t1 Shown unscrambled. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 40 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) The table below lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: * TXEN * TXCLK * CRS The 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for the time periods. Time Period t1 t2 Parameter TXEN Sampled Asserted to CRS Assert TXEN De-Asserted to CRS De-Asserted Conditions Min. 0 0 Typ. 3 3 Max. 4 4 Units Bit times Bit times 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) t2 TXEN TXCLK CRS t1 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 41 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: * TXEN * TXCLK * CRS The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for the time periods. Time Period t1 t2 Parameter TXEN Asserted to CRS Assert TXEN De-Asserted to CRS De-Asserted Conditions Min. 0 0 Typ. - 2 Max. 2 4 Units Bit times Bit times 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) t2 TXEN TXCLK CRS t1 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 42 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M MII Media Independent Interface: Receive Latency The table below lists the significant time periods for the 100M MII/100M Stream Interface receive latency. The time periods consist of timings of signals on the following pins: * TP_RX (that is, TP_RXP and TP_RXN) * RXCLK * RXD (that is, RXD[3:0]) The 100M MII/100M Stream Interface: Receive Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter First Bit of /J/ into TP_RX to /J/ on RXD Conditions 100M MII Min. Typ. - 16 Max. 17 Units Bit times 100M MII/100M Stream Interface: Receive Latency Timing Diagram TP_RX RXCLK RXD t1 Shown unscrambled. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 43 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: * TP_RX (that is, TP_RXP and TP_RXN) * CRS * COL The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time periods. Time Period t1 t2 t3 t4 Parameter First Bit of /J/ into TP_RX to CRS Assert First Bit of /J/ into TP_RX while Transmitting Data to COL Assert First Bit of /T/ into TP_RX to CRS De-Assert First Bit of /T/ Received into TP_RX to COL De-Assert Conditions - Half-Duplex Mode - Half-Duplex Mode Min. Typ. Max. 10 9 13 13 - - - - 14 13 18 18 Units Bit times Bit times Bit times Bit times The IEEE maximum is 20 bit times. The IEEE minimum is 13 bit times, and the maximum is 24 bit times. 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram First bit First bit of /T/ TP_RX t3 t1 CRS COL t2 t4 Shown unscrambled. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 44 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Reset: Power-On Reset The table below lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: * VDD * TXCLK The Power-On Reset Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter VDD 2.7 V to Reset Complete Conditions - Min. 40 Typ. 45 Max. Units 500 ms Power-On Reset Timing Diagram VDD 2.7 V t1 TXCLK Valid IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 45 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Reset: Hardware Reset and Power-Down The table below lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: * REFIN * RESETn * TXCLK The Hardware Reset and Power-Down Timing Diagram shows the timing diagram for the time periods. Time Period t1 t2 t3 Parameter RESETn Active to Device Isolation and Initialization Minimum RESETn Pulse Width RESETn Released to TXCLK Valid Conditions - - - Min. Typ. Max Units . - 200 - 35 60 - - 500 ns ns ms Hardware Reset and Power-Down Timing Diagram REFIN RESETn t1 t2 t3 TXCLK Valid Power Consumption (AC only) IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 46 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10Base-T: Heartbeat Timing (SQE) The table below lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: * TXEN * TXCLK * COL The 10Base-T Heartbeat (SQE) Timing Diagram shows the timing diagram for the time periods. Note: 1. For more information on 10Base-T SQE operations, see the section "10Base-T Operation: SQE Test". 2. In 10Base-T mode, one bit time = 100 ns. Time Period t1 t2 Parameter COL Heartbeat Assertion Delay from TXEN De-Assertion COL Heartbeat Assertion Duration Conditions 10Base-T Half Duplex 10Base-T Half Duplex Min. - - Typ. 850 1000 Max. Units 1500 1500 ns ns 10Base-T Heartbeat (SQE) Timing Diagram TXEN TXCLK COL t1 t2 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 47 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10Base-T: Jabber Timing The table below lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: * TXEN * TP_TX (that is, TP_TXP and TP_TXN) * COL The 10Base-T Jabber Timing Diagram shows the timing diagram for the time periods. Note: For more information on 10Base-T jabber operations, see the section, "10Base-T Operation: Jabber". Time Period t1 t2 Parameter Jabber Activation Time Jabber De-Activation Time Conditions 10Base-T Half Duplex 10Base-T Half Duplex Min. 20 300 Typ. - - Max. Units 35 325 ms ms 10Base-T Jabber Timing Diagram TXEN t1 TP_TX COL t2 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 48 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10Base-T: Normal Link Pulse Timing The table below lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). The 10Base-T Normal Link Pulse Timing Diagram shows the timing diagram for the time periods. Time Period t1 t2 Parameter Normal Link Pulse Width Normal Link Pulse to Normal Link Pulse Period Conditions 10Base-T 10Base-T Min. - 8 Typ. Max. 100 20 - 25 Units ns ms 10Base-T Normal Link Pulse Timing Diagram TP_TXP t1 t2 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 49 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Auto-Negotiation Fast Link Pulse Timing The table below lists the significant time periods for the ICS1894-32 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: * TP_TXP * TP_TXN The Auto-Negotiation Fast Link Pulse Timing Diagram shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN. Time Period t1 t2 t3 t4 t5 t6 Parameter Clock/Data Pulse Width Clock Pulse-to-Data Pulse Timing Clock Pulse-to-Clock Pulse Timing Fast Link Pulse Burst Width Fast Link Pulse Burst to Fast Link Pulse Burst Number of Clock/Data Pulses in a Burst Conditions - - - - - - Min. - 55 110 - 10 15 Typ. 90 60 125 5 15 20 Max. - 70 140 - 25 30 Units ns s s ms ms pulses Auto-Negotiation Fast Link Pulse Timing Diagram Clock Pulse Differential Twisted Pair Transmit Signal Data Pulse Clock Pulse t1 t2 t1 t3 FLP Burst Differential Twisted Pair Transmit Signal t4 FLP Burst t5 IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 50 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER RMII Timing Time Param tcyc t1 t2 Clock Cycle Setup time Hold time Description Min. - 4 2 Typ. 20 Max. Units ns ns ns Transmit Timing REFCLK tCYC t1 t2 TX_EN TXD[1:0] Marking Diagram ICS 1894K32L YYWW ORIGIN ###### Notes: 1. `L' designates Pb (lead) free, RoHS compliant. 1. `YYWW' designates date code. 2. `ORIGIN' desigantes counrty of origin. 3. `######' desigantes the lot number. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 51 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Package Outline and Package Dimensions (32-pin 5mm x 5mm QFN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane Index Area N 1 2 A1 A3 (ND-1)x e (Ref) L N 1 2 Sawn Singulation Top View A E2 (Ref) ND & NE Even e (Typ) If ND & NE 2 are Even (NE-1)x e (Ref) E E2 2 b e D2 2 D2 D (Ref) ND & NE Odd Thermal Base 0.08 C Symbol Min Millimeters Max C A A1 A3 b e N ND NE D x E BASIC D2 E2 L 0.80 1.00 0 0.05 0.20 Reference 0.18 0.30 0.50 BASIC 32 8 8 5.00 x 5.00 3.00 3.3 3.00 3.3 0.3 0.5 Ordering Information Part / Order Number 1894K-32LF 1894K-32LFT Marking see page 51 Shipping Packaging Tubes Tape and Reel Package 32-pin QFN 32-pin QFN Temperature 0 to +70 C 0 to +70 C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT(R) 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 52 ICS1894-32 REV G 020509 ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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